1. Technical Field
Various embodiments of the present disclosure generally relate to semiconductor technology and more particularly to a word line driver for a semiconductor device.
2. Related Art
A semiconductor memory device such as a dynamic random access memory (DRAM) includes a plurality of memory cells for storing data. Each memory cell has a metal oxide semiconductor (MOS) transistor and a capacitor and is coupled to a word line and a 20 bit line. With increasing integration degree, it becomes more difficult to secure stable operation of a MOS transistor. Also, as the gate line width becomes smaller due to improved manufacturing processes, the size of a transistor employed in a memory cell also becomes smaller. As a result, the threshold voltage, the current driving ability and the operating speed of the transistor as well as the information storage time margin of the memory cell itself, approach their safe operation limits. In particular, it is now oftentimes difficult to secure the information storage time of a memory cell, due to gate induced drain leakage (GIDL) which occurs in the area between the source and drain region near the gate electrode. That is because, as the size of the transistor is reduced, the GIDL rapidly increases.
Since memory cells susceptible to GIDL reduce the reliability of a semiconductor memory apparatus, memory cells need to be screened at the initial stage of the fabrication process, in order to secure the quality of the semiconductor memory apparatus. Hence, there is an increased demand for a method capable of effectively screening a memory chip for memory cells susceptible GIDL, during fabrication of the memory chip on a wafer.